The integration of sensor chips in carrier plates, also referred to as microtitre plates, is of particular concern of the present invention. Embodiments of the chip may provide a so-called lab-on-a-chip device, which integrates laboratory functions onto a single chip. An assembly of such chips, which may comprise an array of a plurality of chips on a single carrier, is applicable in a method for determining and/or monitoring electrophysiological properties of ion channels in ion channel-containing structures, typically lipid membrane-containing structures such as cells, by establishing an electrophysiological measuring configuration in which a cell membrane forms a high resistive seal around a measuring electrode, making it possible to determine and monitor a current flow through the cell membrane. The chip is for example useful in a method for analysing the electrophysiological properties of a cell membrane comprising a glycocalyx. The chip may be used in or form part of an apparatus for studying electrical events in cell membranes, such as an apparatus for carrying out patch clamp techniques utilised to study ion transfer channels in biological membranes. In particular, with chips to be used in patch clamp techniques, good adhesion of the cell to the chip is required, so that a high-resistance seal can be obtained between the chip and the cell membrane (a “gigaseal”).
A particular goal in this field has been cheap, disposable chips fabricated of polymeric material, instead of glass or silicon. However, the mechanical properties of polymeric materials are different to those of such materials, and polymeric materials are often not particularly suited to the manufacturing processes used for glass or silicon materials. In addition, polymeric material with a sufficiently high surface smoothness for establishing giga-seals has proven hard to obtain.
WO 03/093494 discloses a biochip for patch clamp detection. U.S. Pat. No. 6,899,800 describes a polymeric electrode for obtaining a gigaohm seal. WO02/059597 discloses a tight electrical seal between a cell and a surface. A mechanically compressible insulating layer is present on the carrier, which compensates for any debris trapped between the cell and the surface.
Manufacturing of chips has required time-consuming and expensive manufacturing techniques (due to the requirements of quality, cleanliness and small-scale for such devices). The present invention aims to overcome problems associated with known processes. In particular, the invention provides improved method for manufacturing of chips comprising polymeric material. In the present invention, macro-dimensional techniques and devices are used to manipulate nano-dimensional articles.